Samsung, TSMC, Intel to form a chip stacking consortium

• The world’s three largest chip giants will form a new consortium along with Qualcomm, Arm, Meta, Microsoft, and several other industry players.
• The new consortium that includes TSMC, Intel and Samsung too, aims to establish a single chip packaging standard, dubbed Universal Chiplet Interconnect Express.

Three of the world’s biggest chipmakers–Taiwan Semiconductor Manufacturing Co(TSMC), Intel and Samsung–will be forming a consortium along with several other leading tech companies, to collaborate on next-generation chip packaging and stacking.

A report by Nikkei last week indicated that besides TSMC, Intel, and Samsung, chip giants like Advanced Micro Devices (AMD), Qualcomm and Arm, Google Cloud, Meta and even Microsoft will be working together to establish an industry standard for advanced chip-packaging technologies. The consortium said it is open to more companies joining.

The chip-packaging sector is dubbed as the next key battleground in the race to build more powerful electronics devices. It makes up the last steps in semiconductor manufacturing before chips are mounted onto print circuit boards and assembled into electronic devices.

“The world’s three biggest chipmakers, along with several other leading tech companies, announced on Thursday that they will form a consortium for collaboration on next-generation chip packaging and stacking,” Nikkei stated. Interestingly, the consortium will also include ASE Technology Holding, the world’s biggest provider of chip packaging and testing services.

Additionally, the new consortium also aims to establish a single chip packaging standard, dubbed Universal Chiplet Interconnect Express (UCIe), to create a new ecosystem and fuel collaboration in the packaging and stacking segments. In short, they will be discussing better ways of combining different types of chips — or so-called chiplets — in one package to create a more powerful chip system.

“UCIe is set to provide a complete “die-to-die” interconnect standard that will make it easy for end users to mix and match chiplet components. This means they will be able to build customized systems-on-a-chip (SoC) using parts from different vendors. An individual chip is called a die before it is packaged,” the report added.

That said, given how chip giants seem to want to work together on chip-packaging standards, it reflects the growing importance of the segment. Given the limits to the number of transistors that can fit on a chip, firms are now trying to optimize their products’ performance by packing and stacking chips in various combinations instead.

“Semiconductor development until now has focused primarily on how to squeeze more transistors onto a chip — in general, more transistors translates to greater computing power. But as the space between transistors has shrunk to just a few nanometers, this approach has become more challenging, leading some to predict the end of Moore’s law, the postulate that the number of transistors on a chip doubles every two years,” Nikkei indicated.

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