• Agentic AI chip design uses software agents to handle multi-step design tasks, and Siemens, Synopsys and Cadence have now tied these tools to TSMC’s A14 process.
• Siemens’ AI agent for fixing design errors comes without figures on time saved or an availability date.

Agentic AI chip design refers to software that can carry out a multi-step chip design task on its own, rather than only answering an engineer’s questions or suggesting changes. An agent can find a problem in a design, decide how to fix it, make the change and check the result, with engineers reviewing the outcome.

The approach is starting to appear in the design flows TSMC supports for its most advanced processes. At the Taiwanese foundry’s Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, California, on September 23, Siemens, Synopsys and Cadence all announced AI agents or agentic workflows developed or enabled with TSMC.

The three companies are the largest makers of electronic design automation (EDA) software used to design chips. Before a chip is manufactured, engineers lay out its circuits, check that the layout follows the foundry’s manufacturing rules, fix any errors and run simulations to confirm it will work. Engineers still do much of that by working through the tools step by step.

The companies’ stated reason for adding agents is design complexity, which they say is rising as chips move to TSMC’s newest processes and to packages that combine several smaller chips. Siemens said its work with TSMC aimed to help customers “manage increasing design complexity” while shortening design cycles.

One example came from Siemens. It said it had worked with TSMC to enable an AI agent that automatically fixes design rule check (DRC) errors across digital and custom chip design flows. DRC is the step where a chip layout is checked against the foundry’s manufacturing rules, and violations generally have to be resolved before the design can go into production. The agent runs on Siemens’ Calibre verification software and is integrated with its Aprisa and Solido tools.

Siemens said the agent was designed to reduce manual work and shorten time to tapeout, the point where a design is finalised and handed to the foundry. The company did not give figures for time saved, name customers using the agent, or say when it would be generally available.

Siemens is also working with TSMC on its Fuse EDA AI Agent, which is designed for long-running, self-verifying design workflows. The company said the Fuse agent uses Nvidia AI technologies to improve token efficiency in those workloads.

Aveek Sarkar, director of TSMC’s ecosystem and alliance management division, said the foundry’s work with partners was focused on automation that engineers could rely on as designs get more complex.

“Our collaboration with OIP partners, such as Siemens, focuses on delivering intelligent, trusted automation that empowers engineers to navigate rising design complexity while achieving stringent performance and energy-efficiency targets,” he said.

A14 certification across all three vendors

The three vendors also announced certifications for A14, TSMC’s next major process node after A16.

Siemens said four of its Calibre verification tools, covering design rule checks, layout-versus-schematic checks, parasitic extraction and reliability checks, were now certified for A14. Certification for its Aprisa place-and-route software and mPower analog software on A14 is still underway.

Synopsys said its digital and analogue design flows had been certified for A14. The company also announced a collaboration with TSMC on agentic AI workflows. These include AI-assisted analogue migration in its Custom Compiler software, large language model-assisted analysis in Fusion Compiler, and a new agentic flow for planning the layout of chiplets in multi-die designs.

Cadence said its digital, signoff and custom analogue flows were now certified for A16 and A14. It added that it was enabling agentic AI chip and 3D-IC design flows with TSMC across the N3, N2, A16 and A14 processes. Cadence said its Virtuoso Studio tools cut design iterations by up to 2.5 times when migrating custom and analogue designs to A16 and A14.

Taiwan’s Global Unichip Corp. (GUC), which designs custom chips for AI accelerators and hyperscale systems, uses Cadence’s tools on TSMC’s leading-edge processes. Cadence said the automation helps GUC reduce schedule risk when working on new process technologies.

Packaging work still in progress

Part of the packaging work announced at the forum is still unfinished. Siemens said certification of its tools for CoWoS-L, a version of the advanced packaging TSMC uses for large AI accelerators, was underway. Its thermal analysis reference flow for TSMC-COUPE, the foundry’s co-packaged optics platform, is still in progress, although its design and verification tools have already been enabled for COUPE features.

Synopsys said its 3DIC Compiler platform could now co-design and simulate integrated voltage regulators on CoWoS. It added that it continues to work with TSMC on co-packaged optics design on COUPE.

No validation standard yet for agentic AI chip design

Brendan Burke, research director for semiconductors at Futurum Group, wrote that TSMC’s involvement changes who carries the risk of agentic automation, describing the foundry as co-developing an agent that modifies design data against its own design rules. He noted, however, that while TSMC certifies EDA tools against its design rules, there is no equivalent process for certifying what an autonomous agent has done to a design.

Burke also wrote that EDA tool readiness for A14 now comes about two years before the node’s production window. He added that thermal and photonics sign-off for wafer-scale packages remains unfinished.