• Singapore’s new advanced packaging consortium with Synopsys brings software licences, not capacity.
• Malaysia’s MAPC has RM185 million to work with, and one member puts a pilot line alone at RM400 million

Synopsys and Singapore’s Agency for Science, Technology and Research (ASTAR) have signed a memorandum of understanding earlier this week on advanced packaging and simulation technologies, with the work running through a new body called the ASTAR IME-Ansys Joint Innovation Consortium for Semiconductor Excellence (JICSE). Under it, Synopsys will provide trial licences to its Ansys simulation software to ASTAR’s Institute of Microelectronics (ASTAR IME) and to up to ten consortium member companies.

The first phase covers mechanical design, modelling and analysis, with named targets including package and wafer warpage, thermo-mechanical stress, solder joint reliability, and moisture-induced failures in multi-chiplet architectures. A*STAR IME will lead the R&D activities. Neither party disclosed a funding figure, a licence period, or a timeline for recruiting member companies.

What the agreement does not involve is equipment, capacity or process development. It sits at the design and verification layer, where problems get caught before anything is physically built. That is a different place on the value chain from where Malaysia put its money four months ago.

Malaysia’s advanced packaging bet starts further down

The Malaysia Advanced Packaging Consortium (MAPC) was launched with an MoU signed at SEMICON Southeast Asia 2026 in May by five local companies: SkyeChip, Inari Technology, FusionAP, Pentamaster Instrumentation and NSW Automation. It carries RM185 million, of which RM92 million is an R&D grant from the Malaysia Science Endowment running over 24 months, matched by RM93 million from industry. 

The target is 7% of the global advanced packaging market by 2035, which the consortium estimates at around US$5 billion in annual revenue. MAPC’s first project is a pilot line capable of assembling packages that integrate HBM4 memory, with SkyeChip designing the HBM4 driver, FusionAP on interposer and substrate technology, Inari on assembly and test, and Pentamaster and NSW Automation supplying test and dispensing equipment.

Kenanga Investment Bank, in a June note following SEMICON SEA, set out the phased roadmap behind it: pilot validation through 2026, a C4 bumping line in Malaysia by 2027, and 2.5D die-on-interposer capability by 2028, with co-packaged optics and finer interconnect pitches further out.

Speaking from the main stage at SEMICON SEA in May, Tan Eng Tong, representing the consortium, put Malaysia at zero on advanced packaging, in a country that is the world’s sixth-largest semiconductor exporter and handles roughly 13% of global assembly, test and packaging work. Science, Technology and Innovation Minister Chang Lih Kang has said the aim is domestic capability within two years, and has pointed to Vietnam closing the gap on the commoditised back-end work Malaysia currently depends on.

The capital requirement is the other constraint. FusionAP has estimated it needs RM400 million to build its own pilot line and a further RM2 billion to scale to high-volume manufacturing, against the RM185 million committed across the whole consortium. SkyeChip, the only listed member to raise recently, took in RM352 million at its Bursa Main Market debut in May.

Hong Leong Investment Bank put advanced packaging gross margins at 40 to 50% in March, against 15 to 20% for traditional packaging, and that spread is what both countries are aiming at. Reaching it from Malaysia’s position means bumping lines, interposers and a customer willing to qualify them. Reaching it from Singapore’s, at least for now, means licence agreements and researchers.

JICSE is also not ASTAR’s first advanced packaging tie-up with a foreign chip supplier. GlobalFoundries signed an MoU in May 2025 giving it access to ASTAR’s R&D facilities and technical support for advanced packaging development and workforce training, with GF supplying equipment to ASTAR in return. Terence Gan, executive director at ASTAR IME, appears in both announcements. The pattern is a national research institute acting as counterparty for foreign vendors wanting a Singapore foothold, with the capital equipment arriving as part of the deal rather than off the state’s balance sheet.

MAPC’s next checkpoints are already public and close. C4 bumping is a 2027 milestone, the government grant runs for 24 months from approval, and HLIB noted in March that an anchor customer and a proven pilot line are still ahead of the consortium. JICSE has published no dates at all.

Corrected on 14 September 2026: an earlier version described MAPC’s first project as an HBM4 pilot line. The consortium is building a pilot line capable of assembling packages that incorporate HBM4 memory, rather than manufacturing HBM4 memory itself.

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